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Appendix A
FPGA Pinouts
This appendix provides the pinouts for the three FPGAs on the Virtex-5 FPGA ML561
Development Board. The toolkit CD shipped with every ML561 contains sample UCFs for
each memory interface. These UCFs are for pinout reference only and do not include other
constraints, like I/O standards.
FPGA #1 Pinout
Table A-1 lists the connections for FPGA #1 (U7).
Table A-1:
FPGA #1 Pinout
Signal Name
Pin
Signal Name
Pin
DDR400 Component Interface
DDR1_A0
DDR1_A1
DDR1_A10
DDR1_A11
DDR1_A12
DDR1_A13
DDR1_A2
DDR1_A3
DDR1_A4
DDR1_A5
DDR1_A6
DDR1_A7
DDR1_A8
DDR1_A9
DDR1_BA0
DDR1_BA1
DDR1_BY0_1_CS_N
DDR1_BY2_3_CS_N
DDR1_CAS_N
Virtex-5 FPGA ML561 User Guide
M32
L33
E33
E32
E34
F33
K32
K34
L34
J34
H34
H33
F34
G33
AK33
AK34
AB33
AC33
AC32
DDR1_CK1_N
DDR1_CK1_P
DDR1_CK2_N
DDR1_CK2_P
DDR1_CKE
DDR1_LB_BK11
DDR1_LB_BK11
DDR1_LB_BK13
DDR1_LB_BK13
DDR1_RAS_N
DDR1_WE_N
DDR1_DM_BY0
DDR1_DM_BY1
DDR1_DM_BY2
DDR1_DM_BY3
DDR1_DQ_BY0_B0
DDR1_DQ_BY0_B1
DDR1_DQ_BY0_B2
DDR1_DQ_BY0_B3
AJ34
AH34
AE34
AF34
AC34
N32
P32
AJ32
AK32
AB32
AD34
AG32
Y32
P34
G32
AP32
AN32
AN33
AN34
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UG199 (v1.2.1) June 15, 2009